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Samsung Reveals New 3D-Memory Roadmap in Bid for AI Tech Lead
Samsung is pivoting to vertically stacked 3D memory to boost AI accelerator performance by eightfold over next-gen HBM5 memory standards.
What: Samsung announced a roadmap for high-bandwidth memory (HBM) that stacks memory chips directly onto AI accelerators, promising 8x performance and 10x memory density compared to HBM5. HBM4 production is scheduled for late 2026.
Why it matters: Memory bandwidth is becoming the primary bottleneck for large-scale AI training, shifting the focus from compute power to efficient 3D-integrated memory architectures.
Decoder
- HBM (High Bandwidth Memory): A high-speed computer memory interface for 3D-stacked DRAM, which provides higher bandwidth while consuming less power than traditional DDR memory.
Original article
Samsung's new memory system vertically stacks high-bandwidth memory on top of AI accelerators. It delivers about eight times the performance and more than 10 times the memory density of next-generation HBM5. Samsung plans to ramp up production of HBM4 in the second half of this year. It has yet to offer a definitive timeline for HBM5 or this future technology.
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